The invention concerns the use of parity signals to validate the transmission of control signals across an I/O limited, high-speed, bidirectional data transmission interface. Two sets of control signals are transferred in opposing directions across the data transmission interface, on each side of the interface parity is generated jointly from the two sets of control signals, and one of the parity determinations is transferred across the data transmission interface to be compared with the other parity determination for validation of the control signals.
In data processing systems, transfer of data between modularized system components can take place under the control of a single processor to which the units interchanging data are connected. The units exchange data across a data transmission interface, with the data exchange proceeding according to a protocol which is implemented by control signals also exchanged between the units
The data interchange units of such a system can be modularized to the degree that each unit is physically replaceable in the system by an identical unit. The most widely employed technique of modularization is that of mounting data interchange units on field replaceable modules such as rack-mounted circuit boards with pluggable interfaces. In modern systems employing such modularization, the bandwidth of a data transmission interface between two modules can climb to hundreds of megahertz, with data being transferred in both directions between the modules.
Conventionally, control signals are employed to implement a data transfer protocol between modules, with control signals having the bandwidth of the data signals. Control signals are normally transferred across a data transmission interface between a pair of modules bidirectionally, by means of two oppositely-directed control signal highways. A control signal highway may comprise a plurality of signal lines which support the parallel transfer of binary digits (bits) referred to as a set of control signals or a control word.
It is important to provide error checking over the control signals transferred between a pair of data interchange units to ensure the detection of errors affecting the control signals that might interfere with the integrity of the data transmission between the units. Another purpose of error checking is to assist in the determination and isolation of malfunctioning units. Once a malfunctioning unit is detected, it can be replaced in the field. The ability to detect and isolate errors at a data interchange unit level supports a repair and maintenance philosophy that accommodates the concept of field replaceable units (FRU).
Sufficient error checking is difficult to implement where the signal paths between FRU's are limited or not available, or when the data rate is high and the physical distance and propagation delays are long between the units. In the context of control lines, error checking for a high-speed, bidirectional data interface is always a difficult task, due to the multidirectional flow of the control lines as they control data transfer across the data transmission interface between a pair of FRU's.
One expects the data transfer rate between FRU's to continue to increase in the future. Increasing the data transfer rate will eventually make the physical length of the overall data transfer path become the limiting factor on data transmission. In addition, as FRU's become increasingly packed with higher density components, implying the requirement for even more high-speed data transfer, input/output (I/O) transfer paths will soon be at a premium, taking into account the limitations on such transfer imposed by the physical dimensions of card connector technology; often there are an insufficient number of data paths available to supply all the data and control interconnections necessary to support the operational functional complement of a field replaceable unit, let alone the error-checking functions.
Given the limitations on data transfer bandwidth and data path availability, the luxury of providing a dedicated error-checking path for each control signal pathway is rapidly becoming unaffordable.
In order to assure the integrity of control signals exchanged between data interchange units over a data transmission interface, it is necessary to allocate I/O resources for the exchange of error checking information in a fashion which is timely enough to maintain the bandwidth of control signal transfer, yet which consumes as little of the valuable I/O resources as possible.